An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, capacitors, and resistors. Commonly known as a “chip” or a “package”, an integrated circuit is generally encased in hard plastic, forming a “package”. The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation has to be precisely controlled to achieve the desired shape and electrical characteristics on the wafer.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A Field Effect Transistor (FET) is a semiconductor device that has controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the shape and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
A fin-Field Effect Transistor (finFET) is a non-planar device in which a source and a drain are connected using a fin-shaped conducting channel (fin) above the insulator layer. In an FET, a gate has a source-side and a drain-side. Generally, a finFET is fabricated as a multi-gate device in which two or more gates are coupled using one or more fin structures by connecting a drain of one gate to the source of another gate using a fin. For example, a fin of a finFET is usually fabricated between two gates such that the source of one gate is on one side of the fin and the drain of the other gate is on an opposite side of the fin. The direction along the lateral length of the fin running from one gate to the other gate is referred to herein as a lateral running direction of the fin.
FinFET structures that are used in semiconductor devices include lateral transport finFET structures and vertical transport finFET structures. In a lateral transport finFET, the fin structure extends laterally along a surface of the semiconductor device when viewed from above. In a vertical transport finFET, the fin structure extends vertically from a surface of the semiconductor device when viewed from above.
Further, vertical transport finFETs are generally fabricated as either nominal vertical transport finFETs or wimpy vertical transport finFETs. In a nominal vertical finFET, an upper surface of the gate of the finFET is below an upper surface of a dielectric material positioned between the gate and the fin. Accordingly, in a nominal vertical transport finFET, the gate does not extend along the entire height of the dielectric. In a wimpy vertical transport finFET, the upper surface of the gate of the finFET is substantially the same height as the upper surface of the dielectric material. Accordingly, in a wimpy vertical transport finFET, the gate extends substantially along the entire height of the dielectric resulting in a slightly larger gate length than for nominal finFET devices. In vertical transport finFET, the gate length (Lg) is dictated by the vertical height of the metal gate. A typical value of Lg for a nominal vertical transport finFET is approximately 15 nm, and a typical value of Lg for a wimpy vertical transport finFET is approximately 20 nm.
The illustrative embodiments recognize that the present methods and techniques for fabricating a finFET suffer from several problems. For example, nominal finFETs and wimpy finFETs each have different performance characteristics and thus it may be desirable to choose either a nominal finFET or a wimpy finFET based upon the particular requirements of a semiconductor device. For example, a larger gate length provides for lower leakage and variability. Due to the slightly larger gate length of the wimpy finFET, the device drive current of the wimpy finFET is lower than that of a nominal finFET. In addition, it may be desirable to include a mixture of nominal finFETs and wimpy finFETs on the same substrate such as in certain complementary metal oxide semiconductor (CMOS) product applications.
The illustrative embodiments further recognize that it is difficult to fabricate nominal vertical finFETs and wimpy vertical finFETs on the same substrate. Therefore, a method for fabricating nominal vertical finFETs and wimpy vertical finFETS on the same substrate would be useful.